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FEATURES Four-Quadrant Multiplication Low Cost 8-Lead Package Complete--No External Components Required Laser-Trimmed Accuracy and Stability Total Error Within 2% of FS Differential High Impedance X and Y Inputs High Impedance Unity-Gain Summing Input Laser-Trimmed 10 V Scaling Reference APPLICATIONS Multiplication, Division, Squaring Modulation/Demodulation, Phase Detection Voltage-Controlled Amplifiers/Attenuators/Filters
X1 1 1 X2 2 1 10V
Low Cost Analog Multiplier AD633
CONNECTION DIAGRAMS 8-Lead Plastic DIP (N) Package
8 +VS
A
7
W
Y1
3
6
Z
Y2
4
1
5
-VS
AD633JN/AD633AN
8-Lead Plastic SOIC (SO-8) Package
PRODUCT DESCRIPTION
Y1
1
The AD633 is a functionally complete, four-quadrant, analog multiplier. It includes high impedance, differential X and Y inputs and a high impedance summing input (Z). The low impedance output voltage is a nominal 10 V full scale provided by a buried Zener. The AD633 is the first product to offer these features in modestly priced 8-lead plastic DIP and SOIC packages. The AD633 is laser calibrated to a guaranteed total accuracy of 2% of full scale. Nonlinearity for the Y-input is typically less than 0.1% and noise referred to the output is typically less than 100 V rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, 20 V/s slew rate, and the ability to drive capacitive loads make the AD633 useful in a wide variety of applications where simplicity and cost are key concerns. The AD633's versatility is not compromised by its simplicity. The Z-input provides access to the output buffer amplifier, enabling the user to sum the outputs of two or more multipliers, increase the multiplier gain, convert the output voltage to a current, and configure a variety of applications. The AD633 is available in an 8-lead plastic DIP package (N) and 8-lead SOIC (R). It is specified to operate over the 0C to +70C commercial temperature range (J Grade) or the -40C to +85C industrial temperature range (A Grade).
1 1 10V A
1
8
X2
Y2
2
7
X1
-VS
3
6
+VS
Z
4
5
W
AD633JR/AD633AR
W= (X1 - X2) (Y1 - Y2) 10V +Z
PRODUCT HIGHLIGHTS
1. The AD633 is a complete four-quadrant multiplier offered in low cost 8-lead plastic packages. The result is a product that is cost effective and easy to apply. 2. No external components or expensive user calibration are required to apply the AD633. 3. Monolithic construction and laser calibration make the device stable and reliable. 4. High (10 M) input resistances make signal source loading negligible. 5. Power supply voltages can range from 8 V to 18 V. The internal scaling voltage is generated by a stable Zener diode; multiplier accuracy is essentially supply insensitive.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD633-SPECIFICATIONS
Model TRANSFER FUNCTION Parameter MULTIPLIER PERFORMANCE Total Error TMIN to TMAX Scale Voltage Error Supply Rejection Nonlinearity, X Nonlinearity, Y X Feedthrough Y Feedthrough Output Offset Voltage DYNAMICS Small Signal BW Slew Rate Settling Time to 1% OUTPUT NOISE Spectral Density Wideband Noise OUTPUT Output Voltage Swing Short Circuit Current INPUT AMPLIFIERS Signal Voltage Range Offset Voltage X, Y CMRR X, Y Bias Current X, Y, Z Differential Resistance POWER SUPPLY Supply Voltage Rated Performance Operating Range Supply Current
(TA = +25 C, V S =
15 V, RL 2 k )
AD633J, AD633A
W=
(X
1
- X 2 Y1 - Y2 10 V
)(
)+Z
Unit % Full Scale % Full Scale % Full Scale % Full Scale % Full Scale % Full Scale % Full Scale % Full Scale mV MHz V/s s V/Hz mV rms V rms V mA V V mV dB A M
Conditions -10 V X, Y +10 V SF = 10.00 V Nominal VS = 14 V to 16 V X = 10 V, Y = +10 V Y = 10 V, X = +10 V Y Nulled, X = 10 V X Nulled, Y = 10 V
Min
Typ 1 3 0.25% 0.01 0.4 0.1 0.3 0.1 5 1 20 2 0.8 1 90
Max 2
1 0.4 1 0.4 50
VO = 0.1 V rms VO = 20 V p-p VO = 20 V
f = 10 Hz to 5 MHz f = 10 Hz to 10 kHz 11
RL = 0 Differential Common Mode VCM = 10 V, f = 50 Hz
30 10 10 60
40
5 80 0.8 10
30 2.0
15 8 Quiescent 4 6 18
V V mA
NOTES Specifications shown in boldface are tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 500 mW Input Voltages3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Operating Temperature Range AD633J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C AD633A . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. 2 8-Lead Plastic DIP Package: JA = 90C/W; 8-Lead Small Outline Package: JA = 155C/W. 3 For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage.
ORDERING GUIDE Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C Package Description Plastic DIP Plastic SOIC 13" Tape and Reel 7" Tape and Reel Plastic DIP Plastic SOIC 13" Tape and Reel 7" Tape and Reel Package Option N-8 SO-8 SO-8 SO-8 N-8 SO-8 SO-8 SO-8
Model AD633AN AD633AR AD633AR-REEL AD633AR-REEL7 AD633JN AD633JR AD633JR-REEL AD633JR-REEL7
-2-
REV. B
AD633
FUNCTIONAL DESCRIPTION
The AD633 is a low cost multiplier comprising a translinear core, a buried Zener reference, and a unity gain connected output amplifier with an accessible summing node. Figure 1 shows the functional block diagram. The differential X and Y inputs are converted to differential currents by voltage-to-current converters. The product of these currents is generated by the multiplying core. A buried Zener reference provides an overall scale factor of 10 V. The sum of (X x Y)/10 + Z is then applied to the output amplifier. The amplifier summing node Z allows the user to add two or more multiplier outputs, convert the output voltage to a current, and configure various analog computational functions.
+VS
voltage controlled amplifiers, and frequency doublers. Note that these applications show the pin connections for the AD633JN pinout (8-lead DIP), which differs from the AD633JR pinout (8-lead SOIC).
Multiplier Connections
Figure 3 shows the basic connections for multiplication. The X and Y inputs will normally have their negative nodes grounded, but they are fully differential, and in many applications the grounded inputs may be reversed (to facilitate interfacing with signals of a particular polarity, while achieving some desired output polarity) or both may be driven.
+15V 0.1 F
X1
1
1 A 1 10V
8
X INPUT
1 2 3 4
X1 X2 Y1 Y2
+VS 8 W7 Z6 -VS 5 0.1 F -15V 10V OPTIONAL SUMMING INPUT, Z W= (X1 - X2) (Y1 - Y2) +Z
AD633JN
X2 2 7 W Y INPUT
Y1
3
6
Z
Y2
4
1
AD633
5
-VS
Figure 3. Basic Multiplier Connections Figure 1. Functional Block Diagram (AD633JN Pinout Shown)
Squaring and Frequency Doubling
Inspection of the block diagram shows the overall transfer function to be:
W=
(X
1
- X 2 Y1 - Y2 10 V
)(
)+Z
(Equation 1)
As Figure 4 shows, squaring of an input signal, E, is achieved simply by connecting the X and Y inputs in parallel to produce an output of E2/10 V. The input may have either polarity, but the output will be positive. However, the output polarity may be reversed by interchanging the X or Y inputs. The Z input may be used to add a further signal to the output.
+15V 0.1 F E
1 2 3 4
ERROR SOURCES
X1 X2 Y1 Y2
+VS 8 W7 Z6 -VS 5 0.1 F -15V W= E2 10V
Multiplier errors consist primarily of input and output offsets, scale factor error, and nonlinearity in the multiplying core. The input and output offsets can be eliminated by using the optional trim of Figure 2. This scheme reduces the net error to scale factor errors (gain error) and an irreducible nonlinearity component in the multiplying core. The X and Y nonlinearities are typically 0.4% and 0.1% of full scale, respectively. Scale factor error is typically 0.25% of full scale. The high impedance Z input should always be referenced to the ground point of the driven system, particularly if this is remote. Likewise, the differential X and Y inputs should be referenced to their respective grounds to realize the full accuracy of the AD633.
+VS
AD633JN
Figure 4. Connections for Squaring
When the input is a sine wave E sin t, this squarer behaves as a frequency doubler, since
(E sin t )
10 V
2
=
50k
300k 1k
50mV TO APPROPRIATE INPUT TERMINAL (E.G. X2, X2, Z)
E2 1 - cos 2 t 20 V
(
)
(Equation 2)
-VS
Equation 2 shows a dc term at the output which will vary strongly with the amplitude of the input, E. This can be avoided using the connections shown in Figure 5, where an RC network is used to generate two signals whose product has no dc term. It uses the identity:
Figure 2. Optional Offset Trim Configuration
APPLICATIONS
The AD633 is well suited for such applications as modulation and demodulation, automatic gain control, power measurement,
cos sin =
1 sin 2 2
(
)
(Equation 3)
REV. B
-3-
AD633
+15V 0.1 F E R
1 2 3 4
R 10k +15V W= R2 3k E2 10V E R 10k +15 0.1 F 0.1 F EX
1 2
X1 X2 Y1 Y2
+VS 8 W7 Z6 -VS 5 0.1 F -15V R1 1k X1 X2 Y1 Y2 +VS 8 W7
AD633JN
C
AD633JN AD711
0.1 F -15
3 4
1N4148 Z6 0.1 F
-VS 5 -15V W = -10V E EX
Figure 5. "Bounceless" Frequency Doubler
At o = 1/CR, the X input leads the input signal by 45 (and is attenuated by 2), and the Y input lags the X input by 45 (and is also attenuated by 2). Since the X and Y inputs are 90 out of phase, the response of the circuit will be (satisfying Equation 3):
W= E
Figure 7. Connections for Division
(10 V )
2
1
E
(sin t + 45) 2
o o
E 2
(sin t - 45)
o
Likewise, Figure 7 shows how to implement a divider using a multiplier in a feedback loop. The transfer function for the divider is
W = - 10 V
(
=
(40 V )
(sin 2 t )
(Equation 4)
) EE
(Equation 6)
+15V 0.1 F
X
which has no dc component. Resistors R1 and R2 are included to restore the output amplitude to 10 V for an input amplitude of 10 V. The amplitude of the output is only a weak function of frequency: the output amplitude will be 0.5% too low at = 0.9 o, and o = 1.1 o.
Generating Inverse Functions
X INPUT
1 2
X1 X2 Y1 Y2
+VS 8 W7 R1 R2 Z6 -VS 5 0.1 F -15V S W= (X1 - X2) (Y1 - Y2) 10V 1k R1, R2 (R1 + R2) R1 100k +S
AD633JN
Y INPUT
3 4
Inverse functions of multiplication, such as division and square rooting, can be implemented by placing a multiplier in the feedback loop of an op amp. Figure 6 shows how to implement a square rooter with the transfer function
W= - 10 V E
Figure 8. Connections for Variable Scale Factor
Variable Scale Factor
(
)
(Equation 5)
for the condition E<0.
R 10k +15V +15 R 10k E 0.1 F 0.1 F
1 2
In some instances, it may be desirable to use a scaling voltage other than 10 V. The connections shown in Figure 8 increase the gain of the system by the ratio (R1 + R2)/R1. This ratio is limited to 100 in practical applications. The summing input, S, may be used to add an additional signal to the output or it may be grounded.
Current Output
X1 X2 Y1 Y2
+VS 8 W7 1N4148 Z6 0.1 F -VS 5 -15V W= -(10V)E
The AD633's voltage output can be converted to a current output by the addition of a resistor R between the AD633's W and Z pins as shown in Figure 9 below. This arrangement forms
+15V 0.1 F X INPUT
1 2 3 4
AD633JN AD711
0.1 F -15
3 4
X1 X2 Y1 Y2
+VS 8 W7 Z6 -VS 5 0.1 F -15V R IO = 1 R 1k (X1 - X2) (Y1 - Y2) 10V R 100k
AD633JN
Y INPUT
Figure 6. Connections for Square Rooting
Figure 9. Current Output Connections
-4-
REV. B
AD633
the basis of voltage controlled integrators and oscillators as will be shown later in this Applications section. The transfer function of this circuit has the form
IO = 1 (X R
1 dB f2 f1 +15V 0.1 F 0 -6dB/OCTAVE OUTPUTA OUTPUT B = f
- X 2 Y1 - Y2 10 V
)(
)
(Equation 7)
CONTROL INPUT EC SIGNAL INPUT ES
1 2 3 4
X1 X2 Y1 Y2
+VS 8 W7 R C -VS 5 0.1 F -15V Z6
OUTPUTB
AD633JN
Linear Amplitude Modulator
1 + T1P 1 + T2P 1 OUTPUT A = 1 + T2P T1 = 1 = RC W1 T2 = 10 1 = W2 ECRC
The AD633 can be used as a linear amplitude modulator with no external components. Figure 10 shows the circuit. The carrier and modulation inputs to the AD633 are multiplied to produce a double-sideband signal. The carrier signal is fed forward to the AD633's Z input where it is summed with the double-sideband signal to produce a double-sideband with carrier output.
Voltage Controlled Low-Pass and High-Pass Filters
Figure 11. Voltage Controlled Low-Pass Filter
dB f1 f2 +15V 0.1 F CONTROL INPUT EC SIGNAL INPUT ES
1 2 3 4
0
f
Figure 11 shows a single multiplier used to build a voltage controlled low-pass filter. The voltage at output A is a result of filtering, ES. The break frequency is modulated by EC, the control input. The break frequency, f2, equals
f2 =
X1 X2 Y1 Y2
+VS 8 W7
OUTPUTB +6dB/OCTAVE OUTPUTA OUTPUT B C OUTPUT A R
AD633JN
Z
6
(20 V ) RC
EC
-VS 5 0.1 F -15V
(Equation 8)
and the rolloff is 6 dB per octave. This output, which is at a high impedance point, may need to be buffered. The voltage at output B, the direct output of the AD633, has same response up to frequency f1, the natural breakpoint of RC filter,
f1 = 1 2 RC
Figure 12. Voltage Controlled High-Pass Filter
Voltage Controlled Quadrature Oscillator
(Equation 9)
then levels off to a constant attenuation of f1/f2 = E C/10.
+15V 0.1 F MODULATION INPUT EM CARRIER INPUT ECsin t
1 2 3 4
X1 X2 Y1 Y2
+VS 8 W7 Z
6
W = 1+
AD633JN
-VS 5 0.1 F -15V
EM 10V
ECsin
t
Figure 13 shows two multipliers being used to form integrators with controllable time constants in a 2nd order differential equation feedback loop. R2 and R5 provide controlled current output operation. The currents are integrated in capacitors C1 and C2, and the resulting voltages at high impedance are applied to the X inputs of the "next" AD633. The frequency control input, EC, connected to the Y inputs, varies the integrator gains with a calibration of 100 Hz/V. The accuracy is limited by the Y-input offsets. The practical tuning range of this circuit is 100:1. C2 (proportional to C1 and C3), R3, and R4 provide regenerative feedback to start and maintain oscillation. The diode bridge, D1 through D4 (1N914s), and Zener diode D5 provide economical temperature stabilization and amplitude stabilization at 8.5 V by degenerative damping. The output from the second integrator (10 V sin t) has the lowest distortion.
AGC AMPLIFIERS
Figure 10. Linear Amplitude Modulator
For example, if R = 8 k and C = 0.002 F, then output A has a pole at frequencies from 100 Hz to 10 kHz for EC ranging from 100 mV to 10 V. Output B has an additional zero at 10 kHz (and can be loaded because it is the multiplier's low impedance output). The circuit can be changed to a high-pass filter Z interchanging the resistor and capacitor as shown in Figure 12 below.
Figure 14 shows an AGC circuit that uses an rms-dc converter to measure the amplitude of the output waveform. The AD633 and A1, 1/2 of an AD712 dual op amp, form a voltage controlled amplifier. The rms dc converter, an AD736, measures the rms value of the output signal. Its output drives A2, an integrator/comparator, whose output controls the gain of the voltage controlled amplifier. The 1N4148 diode prevents the output of A2 from going negative. R8, a 50 k variable resistor, sets the circuit's output level. Feedback around the loop forces the voltages at the inverting and noninverting inputs of A2 to be equal, thus the AGC.
REV. B
-5-
AD633
D5 1N95236 D1 1N914 D2 1N914 R1 1k EC
1 2 3 4
D3 1N914 (10V) cos D4 1N914 X1 X2 Y1 Y2 +VS 8 W7 Z6 -VS 5 0.1 F
4 1
t
+15V 0.1 F +VS 8 W7 Z
6
+15V 0.1 F R2 16k 0.1 F X1 X2 Y1 Y2 R3 330k
C2 0.01 F
R4 16k
AD633JN
2 3
AD633JN
-VS 5 0.1 F -15V
R5 16k
(10V) sin
t
C3 0.1 F
EC f= kHz 10V
-15V
Figure 13. Voltage Controlled Quadrature Oscillator
R2 1k
R3 10k
R4 10k
AGC THRESHOLD ADJUSTMENT +15V 0.1 F
1 2
+15V 0.1 F C1 1F EOUT A1 R5 10k R6 1k +15V 0.1 F
X1 X2 Y1 Y2
+VS 8 W7 Z6 -VS 5 0.1 F -15V C2 0.02 F
1/2 AD712
AD633JN
E
3 4
1 CC COMMON 8 2 VIN 0.1 F +VS 7
AD736
3 CF OUTPUT 6 4 -VS -15V C4 33 F CAV 5
C3 0.2 F
R10 10k A2
R9 10k
1N4148 0.1 F
1/2 AD712
+15V R8 50k OUTPUT LEVEL ADJUST
-15V
Figure 14. Connections for Use in Automatic Gain Control Circuit
-6-
REV. B
Typical Characteristics-AD633
100 0dB = 0.1V rms, RL = 2k 0 CL = 1000pF OUTPUT RESPONSE - dB 90 80 70 60 50 40 30 -30 10k 20 100 TYPICAL FOR X,Y INPUTS
-10
-20 NORMAL CONNECTION
CMRR - dB
CL = 0dB
1M 100k FREQUENCY - Hz
10M
1k
10k FREQUENCY - Hz
100k
1M
Figure 15. Frequency Response
Figure 18. CMRR vs. Frequency
700 V/ Hz NOISE SPECTRAL DENSITY - -40 -20 0 20 40 60 80 100 120 140
1.5
600 BIAS CURRENT - nA
1
500
400
0.5
300
200 -60
0 10
100
TEMPERATURE - C
1k FREQUENCY - Hz
10k
100k
Figure 16. Input Bias Current vs. Temperature (X, Y, or Z Inputs)
Figure 19. Noise Spectral Density vs. Frequency
14 PEAK POSITIVE OR NEGATIVE SIGNAL - Volts
1000
12 OUTPUT, RL 10 ALL INPUTS 8 2k
PK-PK FEEDTHROUGH - Millivolts
Y-FEEDTHROUGH 100
X- FEEDTHROUGH 10
1
6
4
8
10 12 14 16 18 PEAK POSITIVE OR NEGATIVE SUPPLY - Volts
20
0
10
100
1k
10k 100k FREQUENCY - Hz
1M
10M
Figure 17. Input and Output Signal Ranges vs. Supply Voltages
Figure 20. AC Feedthrough vs. Frequency
REV. B
-7-
AD633
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.39 (9.91) MAX
8 5
0.25 0.31 (6.35) (7.87)
1 4
PIN 1 0.10 (2.54) TYP 0.165 0.01 (4.19 0.25) 0.125 (3.18) MIN 0.018 (0.46 0.003 0.03) 0.035 0.01 (0.89 0.25) 0.18 (4.57 0.03 0.76)
0.30 (7.62) REF
0.033 (0.84) SEATING PLANE NOM
0-15
0.11 0.003 (0.28 0.08)
8-Lead Plastic SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
0.0500 (1.27) 0.0160 (0.41)
-8-
REV. B
PRINTED IN U.S.A.
C1480a-0-9/99

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